Operations & Quality
Yield Engineer
About the Role
Drive end-to-end yield learning, defect characterization, and continuous improvement for advanced semiconductor packaging workflows at CG Semi's state-of-the-art OSAT facility.
Responsibilities
- Monitor daily packaging line yield, baseline defect trends, and inline metrology metrics.
- Conduct root-cause failure analysis (FA) on low-yield lots in collaboration with process engineering.
- Develop automated wafer map visualization and defect pareto tracking scripts.
- Participate in product qualification and customer yield report generation.
Qualifications
- Bachelor's or Master's degree in Electrical, Electronics, or Materials Science Engineering.
- 2-5 years of semiconductor manufacturing or OSAT yield engineering experience.
- Hands-on experience with statistical analysis software (JMP, Minitab, or Python).
- Familiarity with wire bond, flip-chip, and wafer-level packaging defect mechanisms.